platform_appscr4.h File Reference

Macros
#define	GCI_CHIPCONTROL_REG   ((volatile uint32_t *)(PLATFORM_GCI_REGBASE(0x200)))
#define	GCI_CHIPCONTROL_REG_0   (0)
#define	GCI_CHIPCONTROL_REG_1   (1)
#define	GCI_CHIPCONTROL_REG_10   (10
#define	GCI_CHIPCONTROL_REG_11   (11
#define	GCI_CHIPCONTROL_REG_2   (2)
#define	GCI_CHIPCONTROL_REG_3   (3)
#define	GCI_CHIPCONTROL_REG_4   (4)
#define	GCI_CHIPCONTROL_REG_5   (5)
#define	GCI_CHIPCONTROL_REG_6   (6)
#define	GCI_CHIPCONTROL_REG_7   (7)
#define	GCI_CHIPCONTROL_REG_8   (8)
#define	GCI_CHIPCONTROL_REG_9   (9)
#define	GCI_CHIPSTATUS_REG   ((volatile uint32_t *)(PLATFORM_GCI_REGBASE(0x204)))
#define	GCI_GPIOCONTROL_REG   ((volatile uint32_t *)(PLATFORM_GCI_REGBASE(0x044)))
#define	GCI_GPIOSTATUS_REG   ((volatile uint32_t *)(PLATFORM_GCI_REGBASE(0x048)))
#define	GCI_GPIOWAKEMASK_REG   ((volatile uint32_t *)(PLATFORM_GCI_REGBASE(0x05C)))
#define	GCI_INDIRECT_ADDR_REG   ((volatile uint32_t *)(PLATFORM_GCI_REGBASE(0x040)))
#define	GCI_WAKEMASK_REG   ((volatile gci_wake_mask_t*)(PLATFORM_GCI_REGBASE(0x1C)))

Detailed Description

Defines BCM43909 APPS CPU core

Macro Definition Documentation

GCI_CHIPCONTROL_REG

#define GCI_CHIPCONTROL_REG   ((volatile uint32_t *)(PLATFORM_GCI_REGBASE(0x200)))

Starting address of chip control registers

GCI_CHIPCONTROL_REG_0

#define GCI_CHIPCONTROL_REG_0   (0)

GPIO 0 - 7

GCI_CHIPCONTROL_REG_1

#define GCI_CHIPCONTROL_REG_1   (1)

GPIO 8 - 15

GCI_CHIPCONTROL_REG_10

#define GCI_CHIPCONTROL_REG_10   (10

Wake count in hibernate

GCI_CHIPCONTROL_REG_11

#define GCI_CHIPCONTROL_REG_11   (11

Hibernate: read select, LPO; also contains clock div, misc bits

GCI_CHIPCONTROL_REG_2

#define GCI_CHIPCONTROL_REG_2   (2)

SDIO, GPIO16, UART0

GCI_CHIPCONTROL_REG_3

#define GCI_CHIPCONTROL_REG_3   (3)

RF SW, SPM, SPI, backplane

GCI_CHIPCONTROL_REG_4

#define GCI_CHIPCONTROL_REG_4   (4)

Drive strength, SDIO, backplane clock,

GCI_CHIPCONTROL_REG_5

#define GCI_CHIPCONTROL_REG_5   (5)

UART RX, RF DISABLE, RF SW CTRL open drain, Function select SPI, strap override, audio pll, DDR clock, mux select mod, bluetooth xtal pullup

GCI_CHIPCONTROL_REG_6

#define GCI_CHIPCONTROL_REG_6   (6)

LPO, JTAG, GPIO hysteresis enable, BT PME to PCIE, GCI clk, NFC xtal clock, RF power down override, GMAC, SDIOD, SDIOH, SPDIF, hysteresis GPIO 8, i2s SPDIF

GCI_CHIPCONTROL_REG_7

#define GCI_CHIPCONTROL_REG_7   (7)

Change detect trigger, negedge change detect, CHIP_UART_RX, clock frequency, SPI and i2c PADs, PAD drive strength

GCI_CHIPCONTROL_REG_8

#define GCI_CHIPCONTROL_REG_8   (8)

app core ready buf req, PAD pull up/down, PADs drive strength, clock hysteresis

GCI_CHIPCONTROL_REG_9

#define GCI_CHIPCONTROL_REG_9   (9)

Function select

GCI_CHIPSTATUS_REG

#define GCI_CHIPSTATUS_REG   ((volatile uint32_t *)(PLATFORM_GCI_REGBASE(0x204)))

Starting address of chip status registers

GCI_GPIOCONTROL_REG

#define GCI_GPIOCONTROL_REG   ((volatile uint32_t *)(PLATFORM_GCI_REGBASE(0x044)))

Starting address of GPIO control registers

GCI_GPIOSTATUS_REG

#define GCI_GPIOSTATUS_REG   ((volatile uint32_t *)(PLATFORM_GCI_REGBASE(0x048)))

Starting address of GPIO status registers

GCI_GPIOWAKEMASK_REG

#define GCI_GPIOWAKEMASK_REG   ((volatile uint32_t *)(PLATFORM_GCI_REGBASE(0x05C)))

Starting address of GPIO wake mask registers

GCI_INDIRECT_ADDR_REG

#define GCI_INDIRECT_ADDR_REG   ((volatile uint32_t *)(PLATFORM_GCI_REGBASE(0x040)))

Register to program the indirect address for indirect register access

GCI_WAKEMASK_REG

#define GCI_WAKEMASK_REG   ((volatile gci_wake_mask_t*)(PLATFORM_GCI_REGBASE(0x1C)))

enable (=1) or disable (=0) wake conditions see gci_wake_mask_t for full bit definitions