hndpmu.c File Reference

Functions
void	si_pmu_pllupd (si_t *sih)
bool	si_pmu_wait_for_res_pending (si_t *sih, osl_t *osh, chipcregs_t *cc, uint usec, bool cond, uint32 *elapsed_time)
int	si_pmu_wait_for_steady_state (si_t *sih, osl_t *osh, chipcregs_t *cc)

Detailed Description

Port of hndpmu.c. Simplified functionality.

Function Documentation

si_pmu_pllupd()

void si_pmu_pllupd

(

si_t *

sih

)

The chip has one or more PLLs/FLLs (e.g. baseband PLL, USB PHY PLL). The settings of each PLL are contained within one or more 'PLL control' registers. Since the PLL hardware requires that changes for one PLL are committed at once, the PMU has a provision for 'updating' all PLL control registers at once.

When software wants to change the any PLL parameters, it withdraws requests for that PLL clock, updates the PLL control registers being careful not to alter any control signals for the other PLLs, and then writes a 1 to PMUCtl.PllCtnlUpdate to commit the changes. Best usage model would be bring PLL down then update the PLL control register.

si_pmu_wait_for_res_pending()

bool si_pmu_wait_for_res_pending	(	si_t *	sih,
		osl_t *	osh,
		chipcregs_t *	cc,
		uint	usec,
		bool	cond,
		uint32 *	elapsed_time )

Wait for usec for the res_pending register to change.

si_pmu_wait_for_steady_state()

int si_pmu_wait_for_steady_state	(	si_t *	sih,
		osl_t *	osh,
		chipcregs_t *	cc )

The algorithm for pending check is that, step1: wait till (res_pending !=0) OR pmu_max_trans_timeout. if max_trans_timeout, flag error and exit. wait for 1 ILP clk [64uS] based on pmu timer, polling to see if res_pending again goes high. if res_pending again goes high, go back to step1. Note: res_pending is checked repeatedly because, in between switching of dependent resources, res_pending resets to 0 for a short duration of time before it becomes 1 again. Note: return 0 is GOOD, 1 is BAD [mainly timeout].